Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_ACS_CNT_INT_ST

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Interpret as L1_CACHE_ACS_CNT_INT_ST

Description

Cache Access Counter Interrupt status register

Fields

L1_IBUS0_OVF_INT_ST	The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0.
L1_IBUS1_OVF_INT_ST	The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1.
L1_IBUS2_OVF_INT_ST	Reserved
L1_IBUS3_OVF_INT_ST	Reserved
L1_BUS0_OVF_INT_ST	The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache.
L1_BUS1_OVF_INT_ST	The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache.
L1_DBUS2_OVF_INT_ST	Reserved
L1_DBUS3_OVF_INT_ST	Reserved

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